The present invention relates to a method of manufacturing a stacked capacitor DRAM cell, and more particularly, to a method of manufacturing a stacked capacitor DRAM cell for forming drain and source polycrystalline silicon on the surface of a substrate.
DRAM (dynamic random access memory) cells are constructed with one transistor in which the drain-source path is connected between a bit line and a cell node, and a storage capacitor which is connected between the cell node and cell plate. As the memory capacity of DRAM devices have increased thereby increasing the DRAM memory density, the size of the memory cells have decreased. In order to maximize the capacity of the storage capacitor with respect to the very limited predetermined area occupied by the DRAM cell, DRAM cell having a three-dimensional capacitor structure, such as, the trench structure and the stacked structure have been developed. Storage capacitors having the trench structure are formed within a groove formed in semiconductor substrate. Storage capacitors having a stacked structure are formed on the semiconductor substrate. A DRAM cell of the stacked capacitor type is easier to manufacture than a DRAM cell of trench capacitor type. Moreover, the stacked capacitor DRAM cell does not include the electrical problems of the trench capacitor type DRAM, such as, leakage and punch-through between one trench and another trench.
FIG. 1 shows a cross sectional view of a conventional stacked capacitor type/DRAM memory cell, the manufacturing method for this DRAM cell will now be explained briefly.
P-type well 2 is formed on P-type substrate 1. A field oxide film layer 4 is formed for isolation between memory cells, and a P+ channel stopper layer 3 is formed under the field oxide film 4. Then, gate oxide film 5 is formed, and doped polycrystalline silicon 6 which forms an electrode of the switching transistor of the memory cell is formed on the gate oxide film 5. At the same time, polycrystalline silicon 7 connected with gate electrode of memory cell being contiguous to the top portion of said field oxide film (4) is formed. Thereafter, an N+ source region 8 and an N+ drain region 9 of switching transistor are formed, and an insulating layer 10 is formed for isolation between said polycrystalline silicon regions 6, 7. Doped storage poly 11 which contacts with selected portion of said source region 8 and forming an electrode of storage capacitor is formed on said polycrystalline silicon regions 6, 7. Dielectric layer 12 of said storage capacitor is formed on the surface of said storage poly 11, and a doped plate poly 13 forming another electrode of said storage capacitor is formed. An insulating film 14 is formed on said plate poly 13, and electrically conductive film 15 which contacts with said drain region 9 and comes to be a bit line is formed.
However, the above-described conventional stacked capacitor cell has had some defects that in case of the insulating film on the source and drain regions being etched in order to form the storage poly and bit line, the said regions get damaged and leakage current is produced.